Microprocessor systems employing multiple processor subsystems including a combination of local and shared memory are becoming increasingly common. Such systems normally have interconnect formed in large part by wide busses carrying data and control information from one subsystem to another.
Busses are at one instant of time controlled by a specific module that is sending information to other modules. A classical challenge in such designs is providing bus arbitration that guarantees that there are no unresolved collisions between separate modules striving for control of the bus.